`ifndef TEST_BASE__SV
`define TEST_BASE__SV

`include "switch_env.sv"

class test_base extends uvm_test;

  	`uvm_component_utils(test_base)
	
 	switch_env env;

function new(string name = "test_base", uvm_component parent = null);
	super.new(name, parent);
	`uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
endfunction: new


virtual function void build_phase(uvm_phase phase);
	super.build_phase(phase);
	`uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
	env = switch_env::type_id::create("env", this);
endfunction: build_phase


virtual function void final_phase(uvm_phase phase);
	super.final_phase(phase);
	//`uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
	//uvm_top.print_topology();
	//factory.print();
	
endfunction: final_phase


virtual task post_main_phase(uvm_phase phase);

	super.post_main_phase(phase);

endtask: post_main_phase


virtual task shutdown_phase(uvm_phase phase);
	super.shutdown_phase(phase);
    
    phase.raise_objection(this); 
	switch_tb.rst_n = 0;
    #100;
    phase.drop_objection(this);
endtask

endclass: test_base
`endif

